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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1995 order number: 270942-005 8xc196kc/8xc196kc20 commercial/express chmos microcontroller 87c196kce16 kbytes of on-chip otprom 83c196kce16 kbytes rom 80c196kceromless y 16 and 20 mhz available y 488 byte register ram y register-to-register architecture y 28 interrupt sources/16 vectors y peripheral transaction server y 1.4 m s 16 x 16 multiply (20 mhz) y 2.4 m s 32/16 divide (20 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y extended temperature available y dynamically configurable 8-bit or 16-bit buswidth y full duplex serial port y high speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y 3 pulse-width-modulated outputs y four 16-bit software timers y 8- or 10-bit a/d converter with sample/hold y hold /hlda bus protocol y otprom one-time programmable version the 80c196kc 16-bit microcontroller is a high performance member of the mcs 96 microcontroller family. the 80c196kc is an enhanced 80c196kb device with 488 bytes ram, 16 and 20 mhz operation and an optional 16 kbytes of rom/otprom. intel's chmos iii process provides a high performance processor along with low power consumption. the 87c196kc is an 80c196kc with 16 kbytes on-chip otprom. the 83c196kc is an 80c196kc with 16 kbytes factory programmed rom. in this document, the 80c196kc will refer to all products unless otherwise stated. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter. with the commercial (standard) temperature option, operational characteristics are guaranteed over the tem- perature range of 0 cto a 70 c. with the extended (express) temperature range option, operational charac- teristics are guaranteed over the temperature range of b 40 cto a 85 c. unless otherwise noted, the specifi- cations are the same for both options. see the packaging information for extended temperature designators.
8xc196kc/8xc196kc20 270942 1 figure 1. 8xc196kc block diagram ioc3 (0ch hwin1 read/write) 270942 45 note: * rsvereserved bits must be e 0 figure 2. 8xc196kc new sfr bit (clkout disable) 2
8xc196kc/8xc196kc20 process information this device is manufactured on px29.5 or px29.9, a chmos iii process. additional process and reliabili- ty information is available in intel's components quality and reliability handbook, order number 210997. 270942 43 example: n87c196kc is 68-lead plcc otprom, 16 mhz. for complete package dimensional data, refer to the intel packaging handbook (order number 240800). note: 1. eproms are available as one time programmable (otprom) only. figure 3. the 8xc196kc family nomenclature table 1. thermal characteristics package i ja i jc type plcc 35 c/w 13 c/w qfp 55 c/w 16 c/w sqfp tbd tbd all thermal impedance data is approximate for static air conditions at 1w of power dissipation. values will change depending on operation conditions and application. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodology. table 2. 8xc196kc memory map description address external memory or i/o 0ffffh 06000h internal rom/otprom or external 5fffh memory (determined by ea ) 2080h reserved. must contain ffh. 207fh (note 5) 205eh pts vectors 205dh 2040h upper interrupt vectors 203fh 2030h rom/otprom security key 202fh 2020h reserved. must contain ffh. 201fh (note 5) 201ah reserved. must contain 20h 2019h (note 5) ccb 2018h reserved. must contain ffh. 2017h (note 5) 2014h lower interrupt vectors 2013h 2000h port 3 and port 4 1fffh 1ffeh external memory 1ffdh 0200h 488 bytes register ram (note 1) 01ffh 0018h cpu sfr's (notes 1, 3, 4) 0017h 0000h notes: 1. code executed in locations 0000h to 01ffh will be forced external. 2. reserved memory locations must contain 0ffh unless noted. 3. reserved sfr bit locations must contain 0. 4. refer to 8xc196kc user's manual for sfr descriptions. 5. warning: reserved memory locations must not be written or read. the contents and/or function of these lo- cations may change with future revisions of the device. therefore, a program that relies on one or more of these locations may not function properly. 3
8xc196kc/8xc196kc20 270942 2 figure 4. 68-lead plcc package 4
8xc196kc/8xc196kc20 270942 40 figure 5. s8xc196kc 80-pin qfp package 5
8xc196kc/8xc196kc20 270942 44 figure 6. 80-pin sqfp package 6
8xc196kc/8xc196kc20 pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are multiple v ss pins, all of which must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp timing pin for the return from powerdown circuit. this pin also supplies the programming voltage on the eprom device. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. reset reset input and open drain output. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses and output low for a data fetch. ea input for memory select (external access). ea equal high causes memory accesses to locations 2000h through 5fffh to be directed to on-chip rom/eprom. ea equal to low causes accesses to those locations to be directed to off-chip memory. also used to enter programming mode. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a signal to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe will go low for external writes to the high byte of the data bus. wrh will go low for external writes where an odd byte is being written. bhe /wrh is activated only during external memory writes. ready ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. when the external memory is not being used, ready has no effect. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2 and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hsi.3, hso.4 and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. port 0 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions in the 80c196kc. pins 2.6 and 2.7 are quasi-bidirectional. 7
8xc196kc/8xc196kc20 pin descriptions (continued) symbol name and function ports 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. hold bus hold input requesting control of the bus. hlda bus hold acknowledge output indicating release of the bus. breq bus request output activated when the bus controller has a pending external memory cycle. pmode determines the eprom programming mode. pact a low signal in auto programming mode indicates that programming is in process. a high signal indicates programming is complete. cpver cummulative program output verification. pin is high if all locations have programmed correctly since entering a programming mode. pale a falling edge in slave programming mode and auto configuration byte programming mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). prog a falling edge in slave programming mode indicates that ports 3 and 4 contain valid programming data (input to slave). pver a high signal in slave programmig mode and auto configuration byte programming mode indicates the byte programmed correctly. ainc auto increment. active low input signal indicates that the auto increment mode is enabled. auto increment will allow reading or writing of sequential eprom locations without address transactions across the pbus for each read or write. 8
8xc196kc/8xc196kc20 electrical characteristics absolute maximum ratings * ambient temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to a 7.0v (1) voltage from ea or v pp to v ss or angnd a 13.00v power dissipation 1.5w (2) note: 1. this includes v pp and ea on rom or cpu only devices. 2. power dissipation is based on package heat transfer lim- itations, not device power consumption. notice: this is a production data sheet. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias commercial temp. 0 a 70 c t a ambient temperature under bias extended temp. b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v angnd analog ground voltage v ss b 0.4 v ss a 0.4 v (1) f osc oscillator frequency (8xc196kc) 8 16 mhz f osc oscillator frequency (8xc196kc20) 8 20 mhz note: 1. angnd and v ss should be nominally at the same potential. dc characteristics (over specified operating conditions) symbol description min typ max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage (note 1) 0.2 v cc a 1.0 v cc a 0.5 v v ih1 input high voltage on xtal 1 0.7 v cc v cc a 0.5 v v ih2 input high voltage on reset 2.2 v cc a 0.5 v v hys hysteresis on reset 300 mv v cc e 5.0v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 2.8 ma 1.5 v i ol e 7ma v ol1 output low voltage 0.8 v i ol ea 0.4 ma in reset on p2.5 (note 2) v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma 9
8xc196kc/8xc196kc20 dc characteristics (over specified operating conditions) (continued) symbol description min typ max units test conditions v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a i oh1 logical 1 output current in reset. b 0.8 ma v ih e v cc b 1.5v on p2.0. do not exceed this or device may enter test modes. i il2 logical 0 input current in reset tbd ma v in e 0.45v on p2.0. maximum current that must be sunk by external device to ensure test mode entry. i ih1 logical 1 input current. a 200 m av in e v cc e 2.4v maximum current that external device must source to initiate nmi. i li input leakage current (std. inputs) g 10 m a0 k v in k v cc b 0.3v i li1 input leakage current (port 0) g 3 m a0 k v in k v ref i tl 1 to 0 transition current (qbd pins) b 650 m av in e 2.0v i il logical 0 input current (qbd pins) b 70 m av in e 0.45v i il1 ports 3 and 4 in reset b 70 m av in e 0.45v i cc active mode current in reset 65 75 ma xtal1 e 16 mhz (8xc196kc) v cc e v pp e v ref e 5.5v i cc active mode current in reset 80 92 ma xtal1 e 20 mhz (8xc196kc20) v cc e v pp e v ref e 5.5v i idle idle mode current (8xc196kc) 17 25 ma xtal1 e 16 mhz v cc e v pp e v ref e 5.5v i idle idle mode current (8xc196kc20) 21 30 ma xtal1 e 20 mhz v cc e v pp e v ref e 5.5v i pd powerdown mode current 8 15 m av cc e v pp e v ref e 5.5v i ref a/d converter reference current 2 5 ma v cc e v pp e v ref e 5.5v r rst reset pullup resistor 6k 65k x v cc e 5.5v, v in e 4.0v c s pin capacitance (any pin to v ss )10pf notes: 1. all pins except reset and xtal1. 2. violating these specifications in reset may cause the part to enter test modes. 3. commercial specifications apply to express parts except where noted. 4. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 5. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0 and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 6. standard inputs include hsi pins, ready, buswidth, rxd/p2.1, extint/p2.2, t2clk/p2.3 and t2rst/p2.4. 7. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 8. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 9. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst clkout i ol :13ma i oh :13ma 10
8xc196kc/8xc196kc20 270942 17 i cc max e 4.13 c frequency a 9ma i cc typ e 3.50 c frequency a 9ma i idle max e 1.25 c frequency a 5ma i idle typ e 0.88 c frequency a 3ma note: frequencies below 8 mhz are shown for reference only; no testing is performed. figure 7. i cc and i idle vs frequency ac characteristics for use over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the system must meet these specifications to work with the 80c196kc: symbol description min max units notes t avyv address valid to ready setup 2 t osc b 68 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2 t osc b 68 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (note 2) t rldv rd active to input data valid t osc b 22 ns (note 2) t cldv clkout low to input data valid t osc b 45 ns t rhdz end of rd to input data float t osc ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc * n, where n e number of wait states. 11
8xc196kc/8xc196kc20 ac characteristics (continued) for user over specified operating conditions. test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 16 mhz the 80c196kc will meet these specifications: symbol description min max units notes f xtal frequency on xtal1 (8xc196kc) 8 16 mhz (note 1) f xtal frequency on xtal1 ( 8xc196kc20) 8 20 mhz (note 1) t osc i/f xtal (8xc196kc) 62.5 125 ns t osc i/f xtal ( 8xc196kc20) 50 125 ns t xhch xtal1 high to clkout high or low a 20 a 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 15 ns t cllh clkout falling edge to ale rising b 5 a 15 ns t llch ale falling edge to clkout rising b 20 a 15 ns t lhlh ale cycle time 4 t osc ns (note 4) t lhll ale high period t osc b 10 t osc a 10 ns t avll address setup to ale falling edge t osc b 15 t llax address hold after ale falling edge t osc b 35 ns t llrl ale falling edge to rd falling edge t osc b 30 ns t rlcl rd low to clkout falling edge a 4 a 30 ns t rlrh rd low period t osc b 5 ns (note 4) t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 2) t rlaz rd low to address float a 5ns t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 a 25 ns t qvwh data stable to wr rising edge t osc b 23 (note 4) t chwh clkout high to wr rising edge b 5 a 15 ns t wlwh wr low period t osc b 20 ns (note 4) t whqx data hold after wr rising edge t osc b 25 ns t whlh wr rising edge to ale rising edge t osc b 10 t osc a 15 ns (note 2) t whbx bhe , inst after wr rising edge t osc b 10 ns t whax ad8 15 hold after wr rising t osc b 30 ns (note 3) t rhbx bhe , inst after rd rising edge t osc b 10 ns t rhax ad8 15 hold after rd rising t osc b 25 ns (note 3) notes: 1. testing performed at 8 mhz. however, the device is static by design and will typically operate below 1 hz. 2. assuming back-to-back bus cycles. 3. 8-bit bus only. 4. if wait states are used, add 2 t osc * n, where n e number of wait states. 12
8xc196kc/8xc196kc20 system bus timings 270942 18 13
8xc196kc/8xc196kc20 ready timings (one wait state) 270942 20 buswidth timings 270942 35 14
8xc196kc/8xc196kc20 hold /hlda timings symbol description min max units notes t hvch hold setup a 55 ns (note 1) t clhal clkout low to hlda low b 15 a 15 ns t clbrl clkout low to breq low b 15 a 15 ns t halaz hlda low to address float a 15 ns t halbz hlda low to bhe , inst, rd ,wr weakly driven a 20 ns t clhah clkout low to hlda high b 15 a 15 ns t clbrh clkout low to breq high b 15 a 15 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe , inst, rd ,wr valid b 10 a 15 ns t cllh clkout low to ale high b 5 a 15 ns note: 1. to guarantee recognition at next clock. dc specifications in hold description min max units weak pullups on adv , rd, 50k 250k v cc e 5.5v, v in e 0.45v wr ,wr l, bhe weak pulldowns on 10k 50k v cc e 5.5v, v in e 2.4 ale, inst 15
8xc196kc/8xc196kc20 270942 36 maximum hold latency bus cycle type internal execution 1.5 states 16-bit external execution 2.5 states 8-bit external execution 4.5 states external clock drive (8xc196kc) symbol parameter min max units 1/t xlxl oscillator frequency 8 16.0 mhz t xlxl oscillator period 62.5 125 ns t xhxx high time 20 ns t xlxx low time 20 ns t xlxh rise time 10 ns t xhxl fall time 10 ns 16
8xc196kc/8xc196kc20 external clock drive (8xc196kc20) symbol parameter min max units 1/t xlxl oscillator frequency 8 20.0 mhz t xlxl oscillator period 50 125 ns t xhxx high time 17 ns t xlxx low time 17 ns t xlxh rise time 8 ns t xhxl fall time 8 ns external clock drive waveforms 270942 21 external crystal connections 270942 41 note: keep oscillator components close to chip and use short, direct traces to xtal1, xtal2 and v ss . when using crystals, c1 e c2 & 20 pf. when using ceramic resonators, consult manufacturer for recommended cir- cuitry. external clock connections 270942 42 note: * required if ttl driver used. not needed if cmos driver is used. ac testing input, output waveforms 270942 22 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 270942 23 for timing purposes a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loaded v oh /v ol level occurs; i ol /i oh e g 15 ma. 17
8xc196kc/8xc196kc20 explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: he high le low ve valid xe no longer valid ze floating signals: ae address be bhe ce clkout de data ge buswidth he hold hae hlda le ale/adv bre breq re rd we wr /wrh /wrl xe xtal1 ye ready qe data out ac characteristicseserial porteshift register mode serial port timingeshift register mode (mode 0) symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge 4 t osc b 50 4 t osc a 50 ns to rising edge (brr t 8002h) t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge 2 t osc b 50 2 t osc a 50 ns to rising edge (brr e 8001h) t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 1 t osc ns waveformeserial porteshift register mode serial port waveformeshift register mode (mode 0) 270942 24 18
8xc196kc/8xc196kc20 a to d characteristics the a/d converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . 10-bit mode a/d operating conditions symbol description min max units t a ambient temperature commercial temp. 0 a 70 c t a ambient temperature extended temp. b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v t sam sample time 1.0 m s (1) t conv conversion time 10 20 m s (1) f osc oscillator frequency (8xc196kc) 8.0 16.0 mhz f osc oscillator frequency (8xc196kc20) 8.0 20.0 mhz note: angnd and v ss should nominally be at the same potential, 0.00v. 1. the value of ad e time is selected to meet these specifications. 10-bit mode a/d characteristics (over specified operating conditions) parameter typical (1) minimum maximum units * notes resolution 1024 1024 levels 10 10 bits absolute error 0 g 3 lsbs full scale error 0.25 g 0.5 lsbs zero offset error 0.25 g 0.5 lsbs non-linearity 1.0 g 2.0 0 g 3 lsbs differential non-linearity error l b 1 a 2 lsbs channel-to-channel matching g 0.1 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 1, 2 feedthrough b 60 db 1 v cc power supply rejection b 60 db 1 input series resistance 750 1.2k x 4 voltage on analog input pin angnd b 0.5 v ref a 0.5 v 5, 6 dc input leakage 0 g 3.0 m a sampling capacitor 3 pf notes: * an ``lsb'' as used here has a value of approxiimately 5 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms). 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if the pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. all conversions performed with processor in idle mode. 19
8xc196kc/8xc196kc20 8-bit mode a/d operating conditions symbol description min max units t a ambient temperature commercial temp. 0 a 70 c t a ambient temperature extended temp. b 40 a 85 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.00 5.50 v t sam sample time 1.0 m s (1) t conv conversion time 7 20 m s (1) f osc oscillator frequency (8xc196kc) 8.0 16.0 mhz f osc oscillator frequency (8xc196kc20) 8.0 20.0 mhz note: angnd and v ss should nominally be at the same potential, 0.00v. 1. the value of ad e time is selected to meet these specifications. 8-bit mode a/d characteristics (over specified operating conditions) parameter typical minimum maximum units * notes resolution 256 256 levels 8 8 bits absolute error 0 g 1 lsbs full scale error g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 1 lsbs differential non-linearity error l b 1 a 1 lsbs channel-to-channel matching g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.003 lsb/ c full scale 0.003 lsb/ c differential non-linearity 0.003 lsb/ c off isolation b 60 db 2, 3 feedthrough b 60 db 2 v cc power supply rejection b 60 db 2 input series resistance 750 1.2k x s4 voltage on analog input pin v ss b 0.5 v ref a 0.5 v 5, 6 dc input leakage 0 g 3.0 m a sampling capacitor 3 pf notes: * an ``lsb'' as used here has a value of approximately 20 mv. (see embedded microcontrollers and processors handbook for a/d glossary of terms). 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. these values may be exceeded if pin current is limited to g 2 ma. 6. applying voltages beyond these specifications will degrade the accuracy of all channels being converted. 7. all conversions performed with processor in idle mode. 20
8xc196kc/8xc196kc20 eprom specifications operating conditions during programming symbol description min max units t a ambient temperature during programming 20 30 c v cc supply voltage during programming 4.5 5.5 v (1) v ref reference supply voltage during programming 4.5 5.5 v (1) v pp programming voltage 12.25 12.75 v (2) v ea ea pin voltage 12.25 12.75 v (2) f osc oscillator frequency during auto and slave 6.0 8.0 mhz mode programming f osc oscillator frequency during 6.0 16.0 mhz run-time programming (8xc196kc) f osc oscillator frequency during 6.0 20.0 mhz run-time programming (8xc196kc20) notes: 1. v cc and v ref should nominally be at the same voltage during programming. 2. v pp and v ea must never exceed the maximum specification, or the device may be damaged. 3. v ss and angnd should nominally be at the same potential (0v). 4. load capacitance during auto and slave mode programming e 150 pf. ac eprom programming characteristics symbol description min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 50 t osc t avll address setup time 0 t osc t llax address hold time 100 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t plph (1) prog pulse width 50 t osc t phll prog high to next pale low 220 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 220 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc note: 1. this specification is for the word dump mode. for programming pulses, use the modified quick pulse algorithm. see user's manual for further information. 21
8xc196kc/8xc196kc20 dc eprom programming characteristics symbol description min max units i pp v pp supply current (when programming) 100 ma note: do not apply v pp until v cc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. eprom programming waveforms slave programming mode data program mode with single program pulse 270942 27 note: p3.0 must be high (``1'') slave programming mode in word dump with auto increment 270942 28 note: p3.0 must be low (``0'') 22
8xc196kc/8xc196kc20 slave programming mode timing in data program with repeated prog pulse and auto increment 270942 29 8xc196kb to 8xc196kc design considerations 1. memory map. the 8xc196kc has 512 bytes of ram/sfrs and an optional 16k of rom/otprom. the extra 256 bytes of ram will reside in locations 100h 1ffh and the extra 8k of rom/otprom will reside in locations 4000h 5fffh. these locations are external memory on the 8xc196kb. 2. the cde pin on the kb has become a v ss pin on the kc to support 16/20 mhz operation. 3. eprom programming. the 8xc196kc has a dif- ferent programming algorithm to support 16k of on-board memory. when performing run-time programming, use the section of code in the 8xc196kc user's guide. 4. once mode entry. the once mode is entered on the 8xc196kc by driving the txd pin low on the rising edge of reset. the txd pin is held high by a pullup that is specified by i oh1 . this pullup must not be overridden or the 8xc196kc will enter the once mode. 5. during the bus hold state, the 8xc196kc weakly holds rd ,wr , ale, bhe and inst in their inactive states. the 8xc196kb only holds ale in its inactive state. 6. a reset pulse from the 8xc196kc is 16 states rather than 4 states as on the 8xc196kb (i.e., a watchdog timer overflow). this provides a longer reset pulse for other devices in the system. 8xc196kc errata 1. missed extint on p0.7. the 80c196kc20 could possibly miss an extint on p0.7. see techbit mc0893. 2. hsi e mode divide-by-eight. see faxback y 2192. 3. ipd hump. see faxback y 2311. 23
8xc196kc/8xc196kc20 data sheet revision history this data sheet is valid for devices with a ``h'', ``l'' or ``m'' at the end of the topside tracking number. the topside tracking number consists of nine characters and is the second line on the top side of the device. data sheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. the following are differences between the 270942-004 and 270942-005 datasheets: 1. removed ``word addressable only'' from port 3 and 4 in table 2. 2. renamed pval to cpver. 3. removed t llyv and t llgv from the waveform diagrams. 4. added hsi e mode divide-by-eight and ipd hump to 8xc196kc errata. the following are important differences between the 270942-002 and 270942-004 data sheets: 1. nmi during pts, qbd port glitch and divide hold/ready erratas were fixed and have been removed from the data sheet. the hsi errata is also removed as this is now considered normal operation. 2. combined 16 and 20 mhz data sheets. data sheet 270924-001 (20 mhz) is now obsolete. 3. added 80-lead sqfp package pinout. 4. added documentation for clkout disable bit. 5. i ja for qfp package was changed to 55 c/w from 42 c/w. 6. i jc for qfp package was changed to 16 c/w from tbd c/w. 7. t sam (min) in 10-bit mode was changed to 1.0 m s from 3.0 m s. 8. t sam (min) in 8-bit mode was changed to 1.0 m s from 2.0 m s. 9. i il1 specification for port 2.0 was renamed i il2 . 10. i il2 (max) is changed to tbd from b 6 ma. 11. i ih1 (max) is changed to a 200 m a from a 100 m a. 12. i ih1 test condition changes to v in e 2.4v from v in e 5.5v. 13. v hys is changed to 300 mv from 150 mv. 14. i cc (typ) at 16 mhz is changed to 65 ma from 50 ma. 15. i cc (max) at 16 mhz is changed to 75 ma from 70 ma. 16. i cc (typ) at 20 mhz is changed to 80 ma from 60 ma. 17. i cc (max) at 20 mhz is changed to 92 ma from 86 ma. 18. i idle (typ) at 16 mhz is changed to 17 ma from 15 ma. 19. i idle (max) at 16 mhz is changed to 25 ma from 30 ma. 20. i idle (typ) at 20 mhz is changed to 21 ma from 15 ma. 21. i idle (max) at 20 mhz is changed to 30 ma from 35 ma. 22. i pd (typ) at 16 mhz is changed to 8 m a from 15 m a. 23. i pd (max) at 16 mhz is changed to 15 m a from tbd. 24. i pd (typ) at 20 mhz is changed to 8 m a from 18 m a. 25. i pd (max) at 20 mhz is changed to 15 m a from tbd. 26. t cldv (max) is changed to t osc b 45 ns from t osc b 50 ns. 27. t llax (min) is changed to t osc b 35 ns from t osc b 40 ns. 28. t chwh (min) is changed to b 5 ns from b 10 ns. 29. t rhax (min) is changed to t osc b 25 ns from t osc b 30 ns. 30. t halaz (max) is changed to a 15 ns from a 10 ns. 31. t halbz (max) is changed to a 20 ns from a 15 ns. 24
8xc196kc/8xc196kc20 32. t hahbv (max) is now specified at a 15 ns, was formerly unspecified. 33. the t llyv and t llgv specifications were removed. these specifications are not required in high-speed systems designs. 34. added extint, p0.7 errata to errata section. the following are the important differences between the -001 and -002 versions of data sheet 270942. 1. express and commercial devices are combined into one data sheet. the express only data sheet 270794-001 is obsolete. 2. removed kb/kc feature set differences, pin definition table, and sfr locations and bitmaps. 3. added programming pin function to package drawings and pin descriptions. 4. changed absolute maximum temperature under bias from 0 cto a 70 cto b 55 cto a 125 c. 5. replaced v oh2 specification with i oh1 and i il1 specifications. 6. added i ih1 specification for nmi pulldown resistors. 7. added maximum hold latency table. 8. added external oscillator and external clock circuit drawings. 9. changed clock drive t xhxx and t xlxx min spec to 20 ns. 10. fixed serial port t xlxh specification. 11. added 8- and 10-bit mode a/d operating conditions tables. 12. specified operating range for sample and convert times. 13. added specification for voltage on analog input pin. 14. put operating conditions for eprom programming into tabular format. 25

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